Achieving low propagation delays and high signaling bandwidth in on-chip global interconnects may be increasingly important to high-performance microprocessors and embedded systems. However, low propagation delays and high signaling bandwidth may be increasingly difficult to achieve due to, for example, a 0.7X reverse-interconnect scaling trend, a fourteen percent increase in die (chip) size, and doubling of clock operating frequency per technology node. Typically, in order to achieve low propagation delays and increased throughput data transfers within computational units on-chip, repeaters are systematically inserted in long global buses. Often, however, repeater insertion is difficult or in some cases cannot be achieved due to placement blockages caused by underlying critical processing units, i.e. lack of space on-chip due to the presence of components that typically cannot be removed. Furthermore, repeater insertion distance may decrease with each technology node due to increased interconnect resistive effects, which may cause the overall improvement in delay and bandwidth to be undermined by an exponential increase in the number of repeaters on-chip and associated driver/repeater power dissipation.
Furthermore, as integrated circuits continue to be aggressively scaled, the number of gates per chip and clock frequencies may continue to increase. The increasing clock rates may exceed, for example, 10 GHz in 2011,and the trend toward larger die sizes exemplified in many microprocessor designs, typically result in longer average interconnect lengths which may increase the electrical distances to be traversed. A solution adopted by the industry to decrease the relative delay of interconnect lines has been to increase the aspect ratio of metal layers to reduce the resistance of on-chip interconnects. However, the increase in aspect ratio with each technology generation may progressively exacerbate signal integrity problems due to increase in the ratio of the coupling capacitance between adjacent conductors to the total capacitance.
Accordingly, cross-talk noise due to inductive and capacitive coupling effects may become increasingly important and may eventually become the dominant problem over local and global propagation delays. The potential problem due to cross-talk may be magnified due to reduced noise margins in modern high performance non-static logic circuits, for example, dynamic circuits with multiple phase clocks and pre-charge logics, which may be used to meet increased speed requirements.
The implementation of alternative solutions, such as using new materials to lower the progressive increase in resistance in interconnects, may show negligible impact on cross-talk noise. The use of low κ dielectrics has proven to reduce cross-talk noise almost proportionally to the reduction in permittivity. Nevertheless, the implementation of low resistivity materials and low κ dielectrics may still be subject to higher production costs. Alternatively, process scaling may impose the need for higher margins of cross-talk noise reduction, which may become progressively difficult on material and interconnect technology.
Other techniques, for example,.are discussed in Clocking Design and Analysis for a 600-MHz Alpha Microprocessor by D. Bailey and B. Benschneider (IEEE Journal of Solid-State Circuits, Vol. 33, no. 11, pp. 1627–1633, November 1998.), the disclosure of which is hereby incorporated herein by reference. In this reference, on-chip power planes are placed between pairs of signal layers, which may sacrifice metal layers to shield signals from interlayer cross-talk. Nevertheless, the dynamic random access memory (DRAM) may pose some significant challenges due to the aggressive aspect ratios used in DRAM interconnects, leading to higher levels of noise coupling.
Accordingly, improved integrated circuit devices and methods that provide low propagation delays and/or high signaling bandwidth in on-chip global interconnects may be desired. Furthermore, integrated circuit devices and methods that may reduce cross-talk noise caused by inductive and/or capacitive coupling effects may also be desired.